OCR Computing Science GCSE – Unit One – Paper One – System Architecture

Download Unit One: systems-architecture-unit-one

System Architecture:

Purpose of the CPU:

The purpose of the CPU is to process data. It is where all the searching, sorting, calculating and decision-making takes place in the computer.

Memory Address Register: Holds the address of the memory location that is going to be accessed.

Program Counter: Holds the memory address of the next instruction.

Memory Data: Register: Holds the data that is to be written or has been retrieved from memory.

Accumulator: Stores the output of the arithmetic and logic unit.

Components of the CPU:

Control Unit:

-Made up of two parts. The clock, which coordinates the CPU’s activity. The decoder, which decodes the programs instructions.

-Manages and monitors hardware on the computer to ensure the correct data goes to the correct hardware.

-Manages the input and output signals ensuring these are dealt with correctly.

-Manages the fetch-decode-execute cycle.

Arithmetic and Logic Unit (ALU);

-Performs all of the arithmetic and logical operations of the CPU:

-Arithmetic part. Performs the calculations on the data. For example: Addition, subtraction, multiplication and division.

-Logic Part. Deals with logical operations. For example: Comparisons such as whether numbers are equal or greater then.

-Boolean operations such as AND, OR and NOT.

Cache:

-Very fast memory inside the CPU which stores regularly used data so the CPU can access it quickly the next time it is needed

-The CPU takes a chunk of data/instructions which is regularly used and keeps it close (cache). This means that it has a constant supply of data to process. This is important as in comparison to cache, accessing the Random Access Memory (Ram) is a very slow operation. This means by storing frequently accessed data and instructions in cache memory, we can avoid the process of accessing RAM.

Fetch, Decode, Execute Cycle:

Fetch Stage: (fetches instruction):

1) Copies the memory address from the program counter to the memory address register

2) Copies the instruction stored in the Memory Address register to the memory data register

3) Increments (Increase) the program counter which points towards to the address of the next instruction to prepare for the next cycle.

Decode Stage: (Decode instruction):

The instruction in the memory address register is then decoded by the control unit. The control unit may then prepare for the next step. This could be by loading values into the MAR or MDR.

Execute Stage (Executes instruction):

The instruction is then performed/data is processed. This could be:

-Load data from memory,

-Write data to memory

-Perform a calculation or logic operation using the ALU

-Change the address in the PC

-Halt a program

Factors that affect the performance of the CPU:

Clock Speed: The number of instructions a single processor core can carry out per second (Hz)

-The average desktop computers, this will be somewhere around 3.5 GHz which is 3.5 billion instructions per second.

The higher the clock speed, the greater the number of instructions that can be carried out per second.

-Some CPUs can be over clocked; this means that the CPU can run at a higher speed than the factory set-rate rate. However, risky if not done probably. It can make a CPU overheat, crash or cause permanent damage to the system. Normally a higher performance cooling systems are needed.

Number of cores:

-Each core in a CPU can process data independently.

-The more cores a CPU has, the more instructions it can carry out at once. This makes it faster to process a batch of data.

-An average desktop computer/smartphone normally have 4 or more cores

Cache Size: Cache is data storage inside the CPU that is much faster than Random Access Memory (RAM)

-A large CPU cache gives the CPU faster access to more data it needs to process

Embedded System: An embedded system is a computer system which is built into another device to support its operation. For example:

-Washing machines

-Digital Cameras

-Sat-Navs

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